CMOS Process Variations: A Critical Operation Point Hypothesis 
CMOS Process Variations: A Critical Operation Point Hypothesis by Stanford
Video Lecture 14 of 22
Not yet rated
Views: 2,825
Date Added: August 24, 2009

Lecture Description

April 2, 2008

Lecture by Janak H. Patel for the Stanford University Computer Systems Colloquium (EE380).

Prevailing understanding of a chip's behavior under large process variations with statistical delay assumptions leads one to conclude that a small number of errors are likely as we progress further down on Moore's Law. This understanding is challenged by a new hypothesis which states that in every large CMOS chip, there exist critical operations points (frequency, voltage, temperature) such that it divides the 3-D space in to two distinct spaces: Error-free operation and Massive errors.

Course Index

Course Description

In this course, Stanford University gives 22 video lectures on the Computer Systems Laboratory Colloquium. This course features weekly speakers on current research and developments in computer systems. Topics touch upon all aspects of computer science and engineering including logic design, computer organization and architecture, software engineering, computer applications, public policy, and the social, business, and financial implications of technology. Frequently the Colloquium provides the first public forum for discussion of new products, discoveries, or ideas. This playlist consists of seminar speakers recorded during the 2007-2008 academic year.

The original name of this course is: Computer Systems Laboratory Colloquium (2007-2008).


There are no comments. Be the first to post one.
  Post comment as a guest user.
Click to login or register:
Your name:
Your email:
(will not appear)
Your comment:
(max. 1000 characters)
Are you human? (Sorry)